According to specifications the functionality of the Delay DPC Card can be broadly divided into the following sub-topics:
1.Conversion of 6 bits of sampler data to 4 bits.
2.Walsh demodulation.
3.Total power read-out (for calibration purposes).
4.Delaying the signal (maximum delay of 150 microseconds).
5.Channel multiplexing (for enabling polarization modes of the correlator and for diagnostics).
6.Support for de-sampling of input data (for allowing high spectral resolution modes).
Each card supports four input pipelines. Each pipeline corresponds to a single polarization. The functions mentioned in earlier section were implemented in following ways:
1.Data conversion:
Conversion of 6 bits of sampler data to 4 bits is done using PROM as a lookup table. It provides the flexibility in changing input to output mapping.
2.Walsh demodulation:
It is implemented inside the FPGA in TBD. Various Walsh sequences can be obtained using a user selectable Walsh word, which depends on the antenna connected to the chain. The start of Walsh sequence is synchronized to a input Walsh synchronisation bit coming from base-band, in addition the start of Walsh sequence can be arbitrarily delayed from sync bit using a Walsh delay word, which is independent from the delay for data.
3.Total power readout:
It is implemented inside FPGA in TBD. The period of total power readout is user selectable and the output is periodically made available and stored in a data buffer from where it can be read by host computer. In addition, the start and stop of accumulation for total power can be synchronized to noise generator on off at the front end, so that the data can be used to determine the Tsys and relative gain variation of each antenna. The total power readout value can be compared with a threshold value decided by more complex algorithms and the result of comparison can be used for flagging data.
4.Delaying the signal and Support for De sampling:
Delay of signal is achieved by using a NCO whose start phase gives the delay of the signal. The output of NCO provides the address of rams where data is stored. The frequency of NCO provides for de-sampling of data. Implementation of NCO is done inside FPGA using TBD.
5.Channel multiplexing:
A complete 4X4 multiplexing is obtained using FPGA.
6.Other functions:
Complex filtering can also be done on data and desired band can be selected for output from the incoming data, by using FIR or other digital filtering technique.
The Delay DPC section can be classified as the following :
1.Circuit Design
2.Description of signals on Daughter Board
3.Bus Communication
4.Resetting of the card